System-on-a-chip (SoC) devices may include one or more central processors, one or more interconnects (or buses), one or more peripheral devices (or upstream devices), and one or more slave devices. Such SoC devices may further include a memory management unit (MMU) coupled to the processor and one or more system MMUs (SMMUs) coupled to the one or more peripheral devices. An SMMU provides address translation services for peripheral device traffic in much the same way that a processor's MMU translates addresses for processor memory accesses.
The main functions of an MMU include address translation, memory protection, and attribute control. Address translation is the translation of an input address to an output address. Translation information is stored in translation tables that the MMU references to perform address translation. An MMU can store completed translations in a translation cache to avoid accessing the translation tables the next time an input address to the same block of memory is received.
Demand misses in the MMU translation cache negatively impact system performance and system costs by causing, for example, increased memory latency (delays), reduced bandwidth utilization, and increased buffering to hide the delays. Present solutions to minimize the number of such demand misses include attempting to “predict” what translations are required in the future and put them in the translation cache. Specifically, these solutions predict that previously used and nearby translations will be required in the future. In order for such prediction scheme to perform well, a high degree of temporal/spatial locality is required. In cases where there is limited spatial/temporal locality, the predictions are often incorrect, and as a result, the prediction schemes perform poorly.